1. Field of the Invention
The present invention relates to a metallization process for manufacturing semiconductor devices. More particularly, the invention relates to a method for adhering metal layers to barrier layers.
2. Background of the Related Art
Consistent and fairly predictable improvement in integrated circuit design and fabrication has been observed in the last decade. One key to successful improvements is the multilevel interconnect technology, which provides the conductive paths between the devices of an integrated circuit (IC) device. The shrinking dimensions of features, presently in the sub-quarter micron and smaller range, such as horizontal interconnects (typically referred to as lines) and vertical interconnects (typically referred to as contacts or vias) in very large scale integration (VLSI) and ultra large scale integration (ULSI) technology, has increased the importance of metal layer deposition and post deposition treatment techniques of metal layers.
The multilevel interconnects that lie at the heart of ultra large scale integration (ULSI) technology require planarization of interconnect features formed in high aspect ratio apertures, including the horizontal and vertical interconnects, and other features. Reliable formation of these interconnects and features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die. As circuit densities increase, the widths of the instruments and other features, as well as the dielectric materials between them, decrease to less than 0.25 xcexcm, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, ie., their height divided by width, increases.
Many traditional deposition processes, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), have difficulty filling structures where the aspect ratio exceed 4:1, and particularly where it exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, nanometer-sized features having high aspect ratios wherein the ratio of feature height to feature width can be 4:1 or higher. Additionally, as the feature widths decrease, the device current remains constant or increases, which results in an increased current density in the feature.
Copper and its alloys are now being considered as an interconnect material in place of aluminum, because copper has a lower resistivity (1.7 xcexcxcexa9-cm compared to 3.1 xcexcxcexa9-cm for aluminum), higher electromigration resistance, and higher current carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increase device speed. Additionally, copper also has good thermal conductivity and is available in a highly pure form. Therefore, copper is becoming a choice metal for filling sub-quarter micron, high aspect ratio interconnect features on semiconductor substrates.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio features (e.g.=4:1 aspect or 0.25xcexc or less size) are limited. In the past, chemical vapor deposition (CVD) and physical vapor deposition (PVD) techniques were the preferred processes for depositing electrically conductive material, typically aluminum, into the contacts, vias, lines, or other features formed on the substrate. However, for copper applications, precursors for CVD copper processes are still being developed, and PVD copper deposition into high aspect ratio features has produced unsatisfactory results because of voids formed in the features. For instance, PVD copper tends to bridge the opening to small features resulting in non-conformal large deposits on the substrate which typically includes voids in the vias and interconnects. As a result of the process limitations of CVD and PVD techniques, electroplating, which had previously been limited to the circuit board fabrication, is being used to fill vias and contacts on semiconductor devices. Thus, efforts are being explored to improve electroplating and other similar processes for use in substrate manufacturing especially in applications with high aspect ratio features.
Metal electroplating is generally known and can be achieved by a variety of techniques. A typical copper electroplating deposition method generally comprises physical vapor depositing a barrier layer over the surface of a substrate having various features formed thereon, chemical vapor depositing or physical vapor depositing a conductive metal seed layer, preferably copper, over the barrier layer, and then electroplating a conductive metal layer over the seed layer to fill the structure/feature.
Copper seed layers are preferably deposited by chemical vapor deposition (CVD) techniques rather than being deposited by physical vapor deposition (PVD) techniques. Although PVD techniques are relatively inexpensive and can provide conformal coverage over a field (the upper or outer most surface of the substrate), however, these same techniques are not well suited for covering the sidewalls, particularly the top corner of the sidewalls, and floor surfaces of high aspect ratio interconnects and other features. This less than desirable coverage results in low resistance to chemical attack and to inter-layer metal diffusion. In contrast, CVD deposited films can provide excellent coverage of sidewalls and maintain a high degree of conformity to the lower surface of high aspect ratio structures.
One problem with the use of copper is that copper diffuses into silicon dioxide, silicon and other dielectric materials. Therefore, conformal barrier layers become increasingly important to prevent copper from diffusing into the dielectric and compromising the integrity of the device. However, due to reliability issues of electromigration resistance and void formation, adhesion between copper and the underlying barrier layer is a major concern in proposed multilevel metallization schemes. With typical copper barrier layers now available, CVD copper has less than desirable adhesion to the barrier layers and has a tendency to delaminate from the sidewalls which leads to agglomeration of the copper layer and formation of voids in the high aspect ratio interconnects.
Therefore there remains a need to develop a metallization process with improved adhesion between barrier layers and subsequently deposited metal layers. Ideally, the improved adhesion method should promote adhesion between refractory metals used as barrier materials and conducting metals, such as copper, used in filling high aspect ratio features.
The invention generally provides a method of improving adhesion of metal layers deposited using chemical vapor deposition or electrochemical deposition techniques to barrier layers. In one aspect of the invention, the deposition process comprises depositing an adhesion layer on a barrier layer formed on the substrate and depositing a metal seed layer on the adhesion layer. The adhesion layer is deposited under conditions, such as reduced substrate temperature, or increased pressure, that minimize agglomeration and form a continuous layer for subsequent void-free filling of features, such as interconnects, on the substrate.
Preferably the adhesion layer comprises copper, platinum, gold, molybdenum, tungsten, nickel, and combinations thereof, deposited by physical vapor deposition at a pressure between about 10 mTorr and about 60 mTorr on a substrate maintained at a temperature below about 300xc2x0 C. Deposition of the adhesion layer preferably occurs at reduced power levels and reduced bias levels to reduce heating of the substrate. A metal seed layer is then deposited on the adhesion layer by chemical vapor deposition or electro-chemical deposition prior to deposition of a metal fill layer.
In one embodiment, the barrier layer preferably comprises titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, and combinations thereof, and may be deposited by physical vapor deposition under conditions that minimize agglomeration and enhance formation of a continuous layer. The metallization process provides for stronger adhesion between refractory barrier layers and seed layers of conducting metals, such as copper, and reduces voids when filling high aspect ratios features.
In another aspect of the invention, a method is provided for processing a substrate by depositing a barrier layer on the substrate, depositing a metal adhesion layer on the barrier layer, and depositing a seed layer, such as copper, on the adhesion layer. The method may further comprise electroplating a conducting metal layer, such as copper, on the seed layer.